1. Field of the Invention
The present invention relates to a semi-conductive substrate, more particularly, to a semiconductive substrate ideally suited for application to high-density and high-performance semiconductor devices.
2. Description of Related Art
Recent research into the development of a SOI (silicon on insulator) mainly comprising a three-dimensional circuit element has been intensively conducted by many industries, and there is a growing drive to develop highly functional semiconductor devices incorporatng a multi-layer semiconductive substrate. While two-dimensional very-large-scale integrated circuits (VLSI) are provided with still faster operating speeds and higher densities, conventional P-N junction isolation methods used for bipolar transistors have limitations not only in the reduction of parasitic capacitance but also into the fine pattern fabrication in the integrated circuits (IC). To overcome the disadvantages, the bipolar transistors isolated by oxidized layers are currently of interest. Nevertheless, there are concerns about the processing of bipolar transistors using the oxidized-layer isolation method, for if they, too, were subjected to still further miniaturizing processes, such as submicron-order processing for example, it is anticipated that the possibilities of realizing yet higher integration and faster operating speeds would eventually face a critical limit, as is the case with the P-N junction isolation method. Likewise, although a wide variety of experiments have actually been made to hasten the early commercial production of sapphire substrates, because of the high cost of the sapphire substrate itself, insufficient electrical characteristics, and inadequate crystallization of the monocrystalline silicon semiconductive layer formed on the sapphire substrate, no sapphire substrate has ever been employed in any of the existing semiconductor devices on a commercial production basis.